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pin connections rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low noise, low drift single-supply operational amplifiers op113/OP213/op413* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features single- or dual-supply operation low noise: 4.7 nv/ ? hz @ 1 khz wide bandwidth: 3.4 mhz low offset voltage: 100 m v very low drift: 0.2 m v/ 8 c unity gain stable no phase reversal applications digital scales multimedia strain gages battery powered instrumentation temperature transducer amplifier general description the o p113 fam ily dual operational a mplifier features the lowest noise and drift of any single-supply amplifier. it has been designed for systems with inte rnal calibration. often these processor based systems are capable of calibrating corrections for offset and gain, but they cannot correct for temperature drifts and noise. optimized for these parameters, the op113 family can be used to take advantage of superior analog perfor- mance combined with digital correction. many systems using internal calibration operate from unipolar supplies, usually ei- ther +5 volts or +12 volts. the op113 family is designed to op- erate from single supplies from +4 volts to +36 volts, and to maintain its low noise and precision performance. the op113 family is unity gain stable and has a typical gain bandwidth product of 3.4 mhz. slew rate is in excess of 1 v/ m s. noise density is a very low 4.7 nv ? hz , and noise in the 0.1 hz to 10 hz band is 120 nv p-p. input offset voltage is guaranteed and offset drift is guaranteed to be less than 0.8 m v/ c. input common-mode range includes the negative supply and to within 1 volt of the positive supply over the full supply range. phase re- versal protection is designed into the op113 family for cases where input voltage range is exceeded. output voltage swings also include the negative supply and go to within 1 volt of the positive rail. the output is capable of sinking and sourcing cur- rent throughout its range and is specified with 600 w loads. digital scales and other strain gage applications benefit from the very low noise and low drift of the op113 family. other appli- cations include use as a buffer or amplifier for both a/d and d/a sigma-delta converters. often these converters have high resolutions requiring the lowest noise amplifier to utilize their full potential. many of these converters operate in either single supply or low supply voltage systems, and attaining the greater signal swing possible increases system performance. * protected by u.s. patent no. 5,146,181. the op113 family is specified for single +5 volt and dual 15 volt operation over the xindextended industrial (C40 c to +85 c) temperature range. they are available in plastic and ce- ramic 8-pin dips, plus soic-8 surface mount packages. contact your local sales office for mil-std-883 data sheet and availability. op113 op113 null ?n a +in a v 1 2 3 4 8 7 6 5 nc v+ out a null null ?n a +in a v nc v+ out a null nc = no connect nc = no connect 1 5 8 4 8-lead epoxy dip (p suffix) 8-lead ceramic dip (s suffix) 8-lead narrow-body so (z suffix) 16-lead narrow-body sol (s suffix) 14-lead epoxy dip (p suffix) 14-lead ceramic dip (y suffix) 1 2 3 4 5 6 7 14 13 12 11 10 9 8 op413 out a ?n a +in a v+ v out b ?n b +in b out d ?n d +in d +in c ?n c out c out c out b op413 out a ?n a +in a v+ ?n b +in b nc v out d ?n d +in d +in c ?n c nc nc = no connect 116 89 OP213 out a ?n a +in a v v+ out b ?n b +in b 1 5 8 4 nc = no connect OP213 out a ?n a +in a v 1 2 3 4 8 7 6 5 v+ out b ?n b +in b 8-lead narrow-body so (s suffix) 8-lead epoxy dip (p suffix) 8-lead ceramic dip (z suffix)
op113/OP213/op413Cspecifications electrical characteristics op113e/op413e op113f/op413f parameter symbol conditions min typ max min typ max units input characteristics offset voltage v os op113 75 150 m v C40 c t a +85 c 125 225 m v OP213 100 250 m v C40 c t a +85 c 150 325 m v op413 125 275 m v C40 c t a +85 c 175 350 m v input bias current i b v cm = 0 v, 240 600 600 na C40 c t a +85 c 700 700 na input offset current i os v cm = 0 v C40 c t a +85 c5050na input voltage range v cm C15 +14 C15 +14 v common-mode rejection cmr C15 v v cm +14 v 100 116 96 db C15 v v cm +14 v, C40 c t a +85 c 97 116 94 db large signal voltage gain a vo op113, OP213, r l = 600 w , C40 c t a +85 c 1 2.4 1 v/ m v op413, r l = 1 k w , C40 c t a +85 c 1 2.4 1 v/ m v r l = 2 k w , C40 c t a +85 c28 2 v/ m v long-term offset voltage 1 v os note 1 150 300 m v offset voltage drift d v os / d t note 2 0.2 0.8 1.5 m v/ c o utput characteristics output voltage swing high v oh r l = 2 k w +14 +14 v r l = 2 k w , C40 c t a +85 c +13.9 +13.9 v output voltage swing low v ol r l = 2 k w C14.5 C14.5 v r l = 2 k w , C40 c t a +85 c C14.5 C14.5 v short circuit limit i sc 40 40 ma power supply power supply rejection ratio psrr v s = 2 v to 18 v 103 120 100 db v s = 2 v to 18 v C40 c t a +85 c 100 120 97 db supply current/amplifier i sy v out = 0 v, r l = , v s = 18 v 2 2 ma C40 c t a +85 c 2.5 2.5 ma supply voltage range v s +4 18 +4 18 v audio performance thd + noise v in = 3 v rms, r l = 2 k w f = 1 khz, 0.0009 0.0009 % voltage noise density e n f = 10 hz 9 9 nv/ ? hz f = 1 khz 4.7 4.7 nv/ ? hz current noise density i n f = 1 khz 0.4 0.4 pa/ ? hz voltage noise e n p-p 0.1 hz to 10 hz 120 120 nv p-p dynamic performance slew rate sr r l = 2 k w 0.8 1.2 0.8 1.2 v/ m s gain bandwidth product gbp 3.4 3.4 mhz channel separation v out = 10 v p-p r l = 2 k w , f = 1 khz 105 105 db settling time t s to 0.01%, 0 v to 10 v step 9 9 m s notes 1 long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 120 c, with an ltpd of 1.3. 2 guaranteed specifications, based on characterization data. specifications subject to change without notice. rev. b C2C (@ v s = 6 15.0 v, t a = +25 8 c unless otherwise noted)
op113/OP213/op413 rev. b C3C electrical characteristics OP213e OP213f parameter symbol conditions min typ max min typ max units input characteristics offset voltage v os op113 125 175 m v C40 c t a +85 c 175 250 m v OP213 150 300 m v C40 c t a +85 c 225 375 m v op413 175 325 m v C40 c t a +85 c 250 400 m v input bias current i b v cm = 0 v, v out = 2 300 650 650 na C40 c t a +85 c 750 750 na input offset current i os v cm = 0 v, v out = 2 C40 c t a +85 c5050na input voltage range v cm 0+4 +4v common-mode rejection cmr 0 v v cm 4 v 93 106 90 db 0 v v cm 4 v, C40 c t a +85 c90 87 db large signal voltage gain a vo op113, OP213, r l = 600 w , 2k 0.01 v v out 3.9 v 2 2 v/ m v op413, r l = 600, 2 k w , 0.01 v v out 3.9 v 1 1 v/ m v long-term offset voltage 1 v os note 1 200 350 m v offset voltage drift d v os / d t note 2 0.2 1.0 1.5 m v/ c o utput characteristics output voltage swing high v oh r l = 600 k w 4.0 4.0 v r l = 100 k w , C40 c t a +85 c 4.1 4.1 v r l = 600 w , C40 c t a +85 c 3.9 3.9 v output voltage swing low v ol r l = 600 w 3.0 3.0 mv r l = 100 k w 3.5 3.5 mv r l = 600 w , C40 c t a +85 c 4.0 4.0 mv r l = 100 k w , C40 c t a +85 c 5.0 5.0 mv short circuit limit i sc 30 30 ma power supply supply current i sy v out = 2.0 v, no load 1.35 1.75 1.75 ma supply current i sy C40 c t a +85 c 2.0 2.0 ma audio performance thd + noise v out = 0 dbu, f = 1 khz 0.001 0.001 % voltage noise density e n f = 10 hz 9 9 nv/ ? hz f = 1 khz 4.7 4.7 nv/ ? hz current noise density i n f = 1 khz 0.45 0.45 pa/ ? hz voltage noise e n p-p 0.1 hz to 10 hz 120 120 nv p-p dynamic performance slew rate sr r l = 2 k w 0.6 0.9 0.6 v/ m s gain bandwidth product gbp 3.5 3.5 mhz settling time t s to 0.01%, 2 v step 5.8 5.8 m s notes 1 long term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 120 c, with an ltpd of 1.3. 2 guaranteed specifications, based on characterization data. specifications subject to change without notice. (@ v s = +5.0 v, t a = +25 8 c unless otherwise noted)
op113/OP213/op413 C4C rev. b wafer test limits parameter symbol conditions limit units offset voltage v os v s = 15 v 100 m v max v cm = 0, v out = 2 v 150 m v max input bias current i b v cm = 0 v 650 na max input offset current i os v cm = 0 v 50 na max input voltage range 1 0 to 4 v min common-mode rejection cmrr 0 v cm 4 v 90 db min power supply rejection ratio psrr v s = 2 v to 18 v 100 m v/v large signal voltage gain a vo r l = 2 k w , v s = 15 v 2 v/ m v min output voltage swing high v oh r l = 600 w 4.0 v min supply current/amplifier i sy v o = 0 v, r l = , v s , v s = 18 v 2.0 ma max/amp notes electrical tests and wafer probe to the limits shown. due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 guaranteed by cmr test. (@ v s = +5.0 v, t a = +25 8 c unless otherwise noted) absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 10 v output short-circuit duration to gnd . . . . . . . . . . indefinite storage temperature range z, y package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +175 c p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c operating temperature range op113/OP213/op413a, b . . . . . . . . . . . . . C55 c to +125 c op113/OP213/op413e, f . . . . . . . . . . . . . . C40 c to +85 c junction temperature range z, y package . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c p, s package . . . . . . . . . . . . . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . +300 c package type u ja u jc units 8-pin cerdip (z) 148 16 c/w 8-pin plastic dip (p) 103 43 c/w 8-pin soic (s) 158 43 c/w 14-pin cerdip (y) 108 16 c/w 14-pin plastic dip (p) 83 39 c/w 16-pin sol (s) 92 27 c/w notes 1 absolute maximum ratings apply to both dice and packaged parts, unless otherwise noted. 2 q ja is specified for the worst case conditions, i.e., q ja is specified for device in socket for cerdip, p-dip, and lcc packages; q ja is specified for device soldered in circuit board for soic package. dice characteristics op113 die size 0.064 x 0.0627 inch, 3,968 sq. mils. substrate (die backside) is connected to v+. transistor count, 66. ordering guide temperature package package model range description option op113ep C40 c to +85 c 8-pin plastic dip n-8 op113es C40 c to +85 c 8-pin soic so-8 op113fp C40 c to +85 c 8-pin plastic dip n-8 op113fs C40 c to +85 c 8-pin soic so-8 OP213ep C40 c to +85 c 8-pin plastic dip n-8 OP213es C40 c to +85 c 8-pin soic so-8 OP213fp C40 c to +85 c 8-pin plastic dip n-8 OP213fs C40 c to +85 c 8-pin soic so-8 op413ep C40 c to +85 c 14-pin plastic dip n-14 op413es C40 c to +85 c 16-pin sol sol-16 op413fp C40 c to +85 c 14-pin pl astic dip n-14 op413fs C40 c to +85 c 16-pin sol sol-16
op113/OP213/op413 rev. b C5C OP213 die size 0.062 x 0.097 inch, 6,014 sq. mils. substrate (die backside) is connected to v+. transistor count, 132. op413 die size 0.106 x 0.106 inch, 10,176 sq. mils. substrate (die backside) is connected to v+. transistor count, 256. applications the op113, OP213 and op413 form a new family of high performance amplifiers that feature precision performance in standard dual supply configurations, and, more importantly, maintain precision performance when a single power supply is used. in addition to accurate dc specifications, it is the lowest noise single supply amplifier available with only 4.7 nv/ ? hz typical noise density. single supply applications have special requirements due to the generally reduced dynamic range of the output signal. single supply applications are often operated at voltages of +5 volts or +12 volts, compared to dual supply applications with supplies of 12 volts or 15 volts. this results in reduced output swings. where a dual supply application may often have 20 volts of sig- nal output swing, single supply applications are limited to at most the supply range, and more commonly several volts below the supply. in order to attain the greatest swing the single supply output stage must swing closer to the supply rails than in dual supply applications. the op113 family has a new patented output stage that allows the output to swing closer to ground, or the negative supply, than previous bipolar output stages. previous op amps had out- puts that could swing to within about ten millivolts of the nega- tive supply in single supply applications. however the op113 family combines both a bipolar and a cmos device in the out- put stage, enabling it to swing to within a few hundred micro- volts of ground. when operating with reduced supply voltages, the input range is also reduced. this reduction in signal range results in reduced signal-to-noise ratio, for any given amplifier. there are only two ways to improve this; increase the signal range or reduce the noise. the op113 family addresses both of these parameters. input signal range is from the negative supply to within one volt of the positive supply over the full supply range. competitive parts have input ranges that are a half a volt to five volts less than this. noise has also been optimized in the op113 family. at 4.7 nv/ ? hz , it is less than one fourth that of competitive devices. phase reversal the op113 family is protected against phase reversal as long as both of the inputs are within the supply ranges. however, if there is a possibility of either input going below the negative supply (or ground in the single supply case), then the inputs should be protected with a series resistor to limit input current to 2 ma. op113 offset adjust the op113 has the facility for external offset adjustment, using the industry standard arrangement. pins 1 and 5 are used in conjunction with a potentiometer of 10 k w total resistance, con- nected with the wiper to vC (or ground in single supply applica- tions). the total adjustment range is about 2 mv using this configuration. adjusting the offset to zero has minimal effect on offset drift (assuming the potentiometer has a tempco of less than 1000 ppm/ c). adjustment away from zero, however, (like all bipolar am- plifiers) will result in a tcv os of approximately 3.3 m v/ c for every millivolt of induced offset. it is, therefore, not generally recommended that this trim be used to compensate for system errors originating outside of the op113. the initial offset of the op113 is low enough that external trimming is almost never required, but if necessary, the 2 mv trim range may be somewhat excessive. reducing the trimming potentiometer to a 2 k w value will give a more reason- able range of 400 m v. 7 4 5 6 1/2 op-213 r1 17.2k w 0.1% output 0 ? 10v f.s. 350 w load cell 8 1 2 3 +15v +10.000v 2n2219a r5 1k w 1 2 4 ad588bd 16 14 15 8 10 6 11 12 13 9 3 ?5v 7 10? cmrr trim 10-turn t.c. less than 50ppm/? ?5v r1 301 w 0.1% r3 17.2k w 0.1% r4 500 w +10.000v 100mv fs a2 1/2 op-213 a1 figure 1. precision load cell scale amplifier
op113/OP213/op413 C6C rev. b application circuits a high precision industrial load-cell scale amplifier the op113 family makes an excellent amplifier for conditioning a load-cell bridge. its low noise greatly improves the signal reso- lution, allowing the load cell to operate with a smaller output range, thus reducing its nonlinearity. figure 1 shows one half of the op113 family used to generate a very stable 10.000 v bridge excitation voltage while the second amplifier provides a differen- tial gain. r4 should be trimmed for maximum common-mode rejection. a low voltage single supply, strain-gage amplifier the true zero swing capability of the op113 family allows the amplifier in figure 2 to amplify the strain-gage bridge accurately even with no signal input while being powered by a single +5 volt supply. a stable 4.000 v bridge voltage is made possible by the rail-to-rail op295 amplifier, whose output can swing to within a millivolt of either rail. this high voltage swing greatly increases the bridge output signal without a corresponding in- crease in bridge input. 8 7 4 6 5 r4 100k w output 0v ? 3.5v +5v 350 w 35mv f.s. 6 2 4 in out gnd ref-43 8 1 4 2 3 1/2 op-295 +5v 2.500v 2n2222a 4.000v 1 2 3 r2 20k w r3 20k w r5 2.10k w r6 27.4 w r g = 2,127.4 w r1 100k w 1/2 op-295 1/2 op-213 r7 20.0k w r8 12.0k w figure 2. single supply strain-gage amplifier a high accuracy linearized rtd thermometer amplifier zero suppressing the bridge facilitates simple linearization of the rtd by feeding back a small amount of the output signal to the rtd (resistor temperature device). in figure 3 the left leg of the bridge is servoed to a virtual ground voltage by amplifier a1, while the right leg of the bridge is also servoed to zero-volt by amplifier a2. this eliminates any error resulting from common-mode voltage change in the amplifier. a three-wire rtd is used to balance the wire resistance on both legs of the bridge, thereby reducing temperature mismatch errors. the 5.000 v bridge excitation is derived from the extremely stable ad588 reference device with 1.5 ppm/ c drift performance. linearization of the rtd is done by feeding a fraction of the output voltage back to the rtd in the form of a current. with just the right amount of positive feedback, the amplifier output will be linearly proportional to the temperature of the rtd. 8 7 4 5 6 v out (10mv/?) +15v r4 100 w ?5v r7 100 w r5 4.02k w r g full scale adjust ?.50v = ?50? +5.00v = +500? r8 49.9k w r9 5k w linearity adjust @1/2 f.s. r w1 r w2 r w3 100 w rtd 1 3 2 a1 1/2op-213 1 2 4 ad588bd 16 14 15 8 10 6 11 12 13 9 3 7 10? ?5v +15v r2 8.25k w r1 8.25k w r3 50 w a2 1/2op-213 figure 3. ultraprecision rtd amplifier to calibrate the circuit, first immerse the rtd in a zero-degree ice bath or substitute an exact 100 w resistor in place of the rtd. adjust the zero adjust potentiometer for a 0.000 v output, then set r9 linearity adjust potentiometer to the middle of its adjustment range. substitute a 280.9 w resistor (equivalent to 500 c) in place of the rtd, and adjust the full-scale adjust potentiometer for a full-scale voltage of 5.000 v. to calibrate out the nonlinearity, substitute a 194.07 w resistor (equivalent to 250 c) in place of the rtd, then adjust the lin- earity adjust potentiometer for a 2.500 v output. check and readjust the full-scale and half-scale as needed. once calibrated, the amplifier outputs a 10 mv/ c temperature coefficient with an accuracy better than 0.5 c over an rtd measurement range of C150 c to +500 c. indeed the amplifier can be calibrated to a higher temperature range, up to 850 c. a high accuracy thermocouple amplifier figure 4 shows a popular k-type thermocouple amplifier with cold-junction compensation. operating from a single +12 volt supply, the op113 familys low noise allows temperature mea- surement to better than 0.02 c resolution from 0 c to 1000 c range. the cold-junction error is corrected by using an inexpen- sive silicon diode as a temperature measuring device. it should be placed as close to the two terminating junctions as physically possible. an aluminum block might serve well as an isothermal system. 8 1 4 3 2 1/2 op-213 0v to 10.00v (0? to 1000?) +12v r9 124k w 2 4 ref-02ez 6 r5 40.2k w r1 10.7k w 10? 0.1? r8 453 w r2 2.74k w r6 200 w +5.000v r4 5.62k w r3 53.6 w d1 1n4148 cu cu k-type thermocouple 40.7?/? +12v 0.1? figure 4. accurate k-type thermocouple amplifier
op113/OP213/op413 rev. b C7C r6 should be adjusted for a zero-volt output with the thermo- couple measuring tip immersed in a zero-degree ice bath. when calibrating, be sure to adjust r6 initially to cause the output to swing in the positive direction first. then back off in the nega- tive direction until the output just stops changing. an ultralow noise, single supply instrumentation amplifier extremely low noise instrumentation amplifiers can be built using the op113 family. such an amplifier that operates off a single supply is shown in figure 5. resistors r1Cr5 should be of high precision and low drift type to maximize cmrr perfor- mance. although the two inputs are capable of operating to zero volt, the gain of C100 configuration will limit the amplifier input common mode to not less than 0.33 v. 1/2 op-213 r1* 10k w r2* 2k w r3* 2k w r4* 10k w r g * (200 w + 12.7 w ) v out v in 1/2 op-213 +5v to +36v *all resistors ?.1%, ?5ppm/ c gain = + 6 20k w r g figure 5. ultralow noise, single supply instrumentation amplifier supply splitter circuit the op113 family has excellent frequency response characteris- tic that makes it an ideal pseudo-ground reference generator as shown in figure 6. the op113 family serves as a voltage fol- lower buffer. in addition, it drives a large capacitor that serves as a charge reservoir to minimize transient load changes, as well as a low impedance output device at high frequencies. the cir- cuit easily supplies 25 ma load current with good settling characteristics. 8 1 4 3 2 1/2 op-113 r3 2.5k w c1 0.1? r4 100 w c2 1? r1 5k w r2 5k w v s + = +5v ? +12v v s + 2 output figure 6. false ground generator low noise voltage reference few reference devices combine low noise and high output drive capabilities. figure 7 shows the op113 family used as a two- pole active filter that band limits the noise of the 2.500 v refer- ence. total noise measures 3 m v p-p. 8 1 4 3 2 1/2 op-113 c2 10? 10k w output +2.500v +5v 3?p-p noise 10? 10k w 6 2 4 in out gnd ref-43 +5v figure 7. low noise voltage reference +5 v only stereo dac for multimedia the op113 familys low noise and single supply capability are ideally suited for stereo dac audio reproduction or sound syn- thesis applications such as multimedia systems. figure 8 shows an 18-bit stereo dac output setup that is powered from a single +5 volt supply. the low noise preserves the 18-bit dynamic range of the ad1868. for dacs that operate on dual supplies, the op113 family can also be powered from the same supplies. 8 1 4 3 2 1/2 op-213 7.68k w 9.76k w 330pf 100pf 7.68k w 7 5 6 1/2 op-213 7.68k w 9.76k w 330pf 100pf 7.68k w 47k w left channel output 47k w right channel output 220? 220? 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ad1868 v l ll dl ck dr lr dgnd vbr vbl vol agnd vor v s +5v supply 18-bit serial reg. 18-bit serial reg. v ref v ref 18-bit dac 18-bit dac figure 8. +5 v only 18-bit stereo dac low voltage headphone amplifiers figure 9 shows a stereo headphone output amplifier for the ad1849 16-bit soundport? stereo codec device. the pseudo- reference voltage is derived from the common-mode voltage generated internally by the ad1849, thus providing a conve- nient bias for the headphone output amplifiers. soundport is a registered trademark of analog devices, inc.
op113/OP213/op413 C8C rev. b 1/2 op-213 +5v 1/2 op-213 5k w optional gain 1k w v ref 1/2 op-213 +5v v ref optional gain 1k w 5k w 29 19 31 10k w 10? lout1l lout1r cmout ad1849 v ref 10? 10k w l volume control r volume control 16 w 220? 47k w headphone left 16 w 220? 47k w headphone right figure 9. headphone output amplifier for multimedia sound codec low noise microphone amplifier for multimedia the op113 family is ideally suited as a low noise microphone preamp for low voltage audio applications. figure 10 shows a gain of 100 stereo preamp for the ad1849 16-bit soundport stereo codec chip. the common-mode output buffer serves as a phantom power driver for the microphones. +5v 1/2 op-213 10k w 50 w 10? 20 w 100 w 10k w +5v 1/2 op-213 20 w 50 w 10? 10k w 1/2 op-213 10k w 100 w 15 17 minl minr 19 cmout ad1849 left electret condense r mic input right electret condense r mic input figure 10. low noise stereo microphone amplifier for multimedia sound codec precision voltage comparator with its pnp inputs and zero volt common-mode capability, the op113 family can make useful voltage comparators. there is only a slight penalty in speed in comparison to ic comparators. however, the significant advantage is its voltage accuracy. for example, v os can be a few hundred microvolts or less, com- bined with cmrr and psrr exceeding 100 db, while operat- ing on 5 v supply. standard comparators like the 111/311 family operate on 5 volts, but not with common-mode at ground, nor with offset below 3 mv. indeed no commercially available single supply comparator has a v os less than 200 m v. figure 11 shows the op113 family response to a 10 mv over- drive signal when operating in open loop. the top trace shows the output rising edge has a 15 m s propagation delay, while the bottom trace shows a 7 m s delay on the output falling edge. this ac response is quite acceptable in many applications. 1/2 op-113 +5v 100 w 25k 0v ?.5v +2.5v t r = t f = 5ms ?0mv overdrive 10 90 100 0% 2v 2v 5? figure 11. precision comparator the low noise and 250 m v (maximum) offset voltage enhance the overall dc accuracy of this type of comparator. note that zero crossing detectors and similar ground referred comparisons can be implemented even if the input swings to C0.3 volts below ground.
op113/OP213/op413 rev. b C9C 100 0 50 60 20 ?0 40 ?0 80 40 30 20 10 0 ?0 ?0 ?0 input offset voltage, v os ?? units v s = ?5v t a = +25 c 400 x op amps plastic pkg figure 12a. op113 input offset (v os ) distribution @ 15 v 500 0 100 300 100 ?0 200 ?00 400 80 60 40 20 0 ?0 ?0 ?0 input offset voltage, v os ?? units v s = ?5v t a +25 c 896 (plastic) x op amps figure 12b. OP213 input offset (v os ) distribution @ 15 v 500 0 140 300 100 ?0 200 ?0 400 120 100 80 60 40 20 0 ?0 input offset voltage, v os ?? units v s = ?5v t a = +25 c 1220 x op amps plastic pkg figure 12c. op413 input offset (v os ) distribution @ 15 v 150 0 1.0 90 30 0.1 60 0 120 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 tcv os ?? units v s = ?5v ?0 c t a +85 c 400 x op amps plastic pkg figure 13a. op113 temperature drift (tcv os ) distribution @ 15 v 500 0 1.0 300 100 0.1 200 0 400 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 tcv os ?? units v s = ?5v ?0 c t a +85 c 896 (plastic) x op amps figure 13b. OP213 temperature drift (tcv os ) distribution @ 15 v tcv os ?? units 600 0 1.0 300 100 0.1 200 0 500 400 0.9 0.7 0.6 0.5 0.8 0.4 0.3 0.2 v s = ?5v ?0 c t a +85 c 1220 x op amps plastic pkg figure 13c. op413 temperature drift (tcv os ) distribution @ 15 v
op113/OP213/op413 C10C rev. b 1000 0 125 600 200 ?0 400 800 100 75 50 25 0 ?5 temperature ? c input bias current ?na v cm = 0v ?5 v s = 5.0v v cm = 2.5v v s = ?5v v cm = 0v figure 14. op113 input bias current vs. temperature 5.0 3.0 125 4.5 3.5 ?0 4.0 75 100 50 25 0 ?5 temperature ? c positive output swing ?volts v s = +5.0v 2.0 0 1.5 0.5 1.0 negative output swing ?volts ?wing r l = 2k ?wing r l = 600 ?5 +swing r l = 2k +swing r l = 600 w w w w figure 15. output swing vs. temperature and r l @ +5 v 10 100 10m 1m 100k 10k 1k frequency ?hz 105 60 40 20 0 ?0 ?0 ?0 ?0 ?00 ?20 channel separation ?db v s = ?5v t a = +25? figure 16. channel separation 500 0 +125 300 100 ?0 200 400 +100 +75 +50 +25 0 ?5 temperature ? c input bias current ?na v s = ?5v v s = +5.0v ?5 figure 17. OP213 input bias current vs. temperature 15.0 ?5.0 125 ?3.5 ?4.5 ?0 ?4.0 ?5 13.0 12.5 13.5 14.0 14.5 100 75 50 25 0 ?5 temperature ? c positive output swing ?volts v s = 15v ?wing r l = 600 w ?wing r l = 2k w +swing r l = 2k w +swing r l = 600 w figure 18. o utput swing vs. temperature and r l @ 15 v 20 0 +125 6 2 ?0 4 12 8 10 14 16 18 +100 +75 +50 +25 0 ?5 temperature ? c open loop gain ?v/ m v v s = +5.0v v o = 3.9v ?5 r l = 2k w r l = 600 w figure 19. open-loop gain vs. temperature @ +5 v
op113/OP213/op413 rev. b C11C 12.5 0 125 ?0 2.5 7.5 5.0 10.0 100 75 50 25 0 ?5 temperature ? c open-loop gain ?v/? r l = 2k r l = 600 v s = ?5v v o = ?0v ?5 r l = 1k w w w figure 20. op413 open-loop gain vs. temperature 100 40 ?0 10k 10m 1m 100k 1k 20 0 60 80 frequency ?hz open-loop gain ?db 90 225 135 180 45 0 phase ?degrees v+ = 5v v?= 0v t a = +25 c gain phase q m = 57 figure 21. open-loop gain, phase vs. frequency @ +5 v 50 30 ?0 10k 10m 1m 100k 1k 40 10 20 ?0 0 frequency ?hz closed-loop gain ?db v+ = 5v v?= 0v t a = +25 c a v = +100 a v = +10 a v = +1 figure 22. closed-loop gain vs. frequency @ +5 v 10 0 +125 3 1 ?0 2 6 4 5 7 8 9 +100 +75 +50 +25 0 ?5 temperature ? c open loop gain ?v/? r l = 2k r l = 600 v s = ?5v v o = ?0v ?5 w w figure 23. OP213 open-loop gain vs. temperature 100 40 ?0 10k 10m 1m 100k 1k 20 0 60 80 frequency ?hz open-loop gain ?db 90 225 135 180 45 0 phase ?degrees t a = +25 c v s = ?5v gain phase q m = 72 figure 24. open-loop gain phase vs. frequency @ 15 v 50 30 ?0 10k 10m 1m 100k 1k 40 10 20 ?0 0 frequency ?hz closed-loop gain ?db a v = +100 a v = +10 a v = +1 t a = +25? v s = ?5v figure 25. closed-loop gain vs. frequency @ 15 v
op113/OP213/op413 C12C rev. b 70 50 125 65 55 ?0 60 75 100 50 25 0 ?5 temperature ? c phase margin ?degrees v+ = 5v v?= 0v 5 1 4 2 3 gain-bandwidth product ?mhz ?5 gbw q m figure 26. gain bandwidth product and phase margin vs. temperature @ +5 v 30 15 0 110 1k 100 10 5 20 25 frequency ?hz voltage noise density ?nv/ hz t a = +25? v s = ?5v figure 27. voltage noise density vs. frequency 140 100 0 1k 1m 100k 10k 100 120 60 80 20 40 frequency ?hz common-mode rejection ?db v+ = 5v v?= 0v t a = +25 c figure 28. c ommon-mode rejection vs. frequency @ +5 v 70 50 125 65 55 ?0 60 75 100 50 25 0 ?5 temperature ? c phase margin ?degrees v s = ?5v 5 1 4 2 3 gain-bandwidth product ?mhz ?5 gbw q m figure 29. gain bandwidth product and phase margin vs. temperature @ 15 v 3.0 1.5 0 110 1k 100 1.0 0.5 2.0 2.5 frequency ?hz voltage noise density ?pa/ hz t a = +25? v s = ?5v figure 30. current noise density vs. frequency 140 100 0 1k 1m 100k 10k 100 120 60 80 20 40 frequency ?hz common-mode rejection ?db t a = +25 c v s = ?5v figure 31. common-mode rejection vs. frequency @ 15 v
op113/OP213/op413 rev. b C13C 140 100 0 1k 1m 100k 10k 100 120 60 80 20 40 frequency ?hz power supply rejection ?db t a = +25 c v s = ?5v +psrr ?srr figure 32. power supply rejection vs. frequency @ 15 v 6 3 0 10k 10m 1m 100k 1k 2 1 4 5 frequency ?hz maximum output swing ?volts v s = +5v r l = 2k w t a = +25 c a vcl = +1 figure 33. maximum output swing vs. frequency @ +5 v 50 0 500 15 5 100 10 0 30 20 25 35 40 45 400 300 200 load capacitance ?pf overshoot ?% negative edge positive edge v s = +5v r l = 2k w v in = 100mvp? t a = +25 c a vcl = +1 figure 34. small signal overshoot vs. load capacitance @ +5 v 40 20 0 1k 1m 100k 10k 100 10 30 t a = +25 c v s = ?5v frequency ?hz impedance ? w a v = +100 a v = +10 a v = +1 figure 35. closed-loop output impedance vs. frequency @ +15 v 30 15 0 10k 10m 1m 100k 1k 10 5 20 25 frequency ?hz maximum output swing ?volts v s = ?5v r l = 2k t a = +25 c a vcl = +1 w figure 36. maximum output swing vs. frequency @ 15 v 20 0 500 6 2 100 4 0 12 8 10 14 16 18 400 300 200 load capacitance ?pf overshoot ?% negative edge positive edge v s = ?5v r l = 2k v in = 100mvp? t a = +25 c a vcl = +1 w figure 37. small signal overshoot vs. load capacitance @ 15 v
op113/OP213/op413 C14C rev. b 2.0 0 125 1.5 0.5 ?0 1.0 75 100 50 25 0 ?5 temperature ? c slew rate ?v/ m s v s = +5, 0 +0.5v v out +4.0v ?lew rate +slew rate ?5 figure 38. slew rate vs. temperature @ +5 v (0.5 v v out +4.0 v) 10 100 0% 90 20mv 1s figure 39. input voltage noise @ 15 v (20 nv/div) 0.1 ?10hz a v = 1000 t out a v = 100 909 w 100 w figure 40. noise test diagram 2.0 0 125 1.5 0.5 ?0 1.0 75 100 50 25 0 ?5 temperature ? c slew rate ?v/? v s = ?5v v out = ?0v ?lew rate +slew rate ?5 figure 41. slew rate vs. temperature @ 15 v (C10 v v out +10.0 v) 10 0% 100 90 20mv 1s figure 42. input voltage noise @ +5 v (20 nv/ div) 5 0 +125 3 1 ?0 2 4 +100 +75 +50 +25 0 ?5 temperature ? c supply current ?ma v s = ?8v v s = ?5v v s = +5.0v ?5 figure 43. supply current vs. temperature
op113/OP213/op413 rev. b C15C * second current noise source dn5 27 28 din dn6 28 29 din vn5 27 0 dc 2 vn6 0 29 dc 2 * * gain stage & dominant pole at .2000e+01 hz g2 34 36 19 20 2.65eC04 r7 34 36 39e+06 v3 35 4 dc 6 d4 36 35 dx vb2 34 4 1.6 * * supply/2 generator isy 7 4 0.2eC3 r10 7 60 40e+3 r11 60 4 40e+3 c3 60 0 1eC9 * * cmrr stage & pole at 6 khz ecm 50 4 poly(2) 3 60 2 60 0 1.6 0 1.6 ccm 50 51 26.5eC12 rcm1 50 51 1e6 rcm2 51 4 1 * * output stage r12 37 36 1e3 r13 38 36 500 c4 37 6 20eC12 c5 38 39 20eC12 m1 39 36 4 4 mn l=9eC6 w=1000eC6 ad=15eC9 as=15eC9 m2 45 36 4 4 mn l=9eC6 w=1000eC6 ad=15eC9 as=15eC9 d5 39 47 dx d6 47 45 dx q3 39 40 41 qpa 8 vb 7 40 dc 0.861 r14 7 41 375 q4 41 7 43 qna 1 r17 7 43 15 q5 43 39 6 qna 20 q6 46 45 6 qpa 20 r18 46 4 15 q7 36 46 4 qna 1 m3 6 36 4 4 mn l = 9eC6 w=2000eC6 ad=30eC9 as=30eC9 * * nonlinear models used * .model dx d (is=1eC15) .model dy d (is=1eC15 bv=7) .model pnp1 pnp (bf=220) .model den d(is=1eC12 rs=1016 kf=3.278eC15 af=1) .model din d(is=1eC12 rs=100019 kf=4.173eC15 af=1) .model qna npn(is=1.19eC16 bf=253 vaf=193 var=15 rb=2.0e3 + irb=7.73eC6 rbm=132.8 re=4 rc=209 cje=2.1eC13 vje=0.573 + mje=0.364 cjc=1.64eC13 vjc=0.534 mjc=0.5 cjs=1.37eC12 + vjs=0.59 mjs=0.5 tf=0.43eC9 ptf=30) .model qpa pnp(is=5.21eC17 bf=131 vaf=62 var= 15 rb=1.52e3 + irb=1.67eC5 rbm=368.5 re=6.31 rc=354.4 cje=1.1eC13 + vje=0.745 mje=0.33 cjc=2.37eC13 vjc=0.762 mjc=0.4 + cjs=7.11eC13 vjs=0.45 mjs=0.412 tf=1.0eC9 ptf=30) .model mn nmos(level=3 vto=1.3 rs=0.3 rd=0.3 tox=8.5eC8 + ld=1.48eC6 wd=1eC6 n sub=1.53e16 uo=650 d elta=10 vmax=2e5 + xj=1.75eC6 kappa=0.8 eta=0.066 theta=0.01 tpg=1 cj=2.9eC4 + pb=0.837 mj=0.407 cjsw=0.5eC9 mjsw=0.33) * .ends op113 family 9v 9v +in ?n out figure 44. OP213 simplified schematic *op113 family spice macro-model 9/92, rev. a * jcn/pmi *copyright 1992 by analog devices, inc. * *node assignments * * noninverting input * inverting input * positive supply * negative supply * output * .subckt op113 family 3 2 7 4 6 * * input stage r3 4 19 1.5e3 r4 4 20 1.5e3 c1 19 20 5.31eC12 i1 7 18 106eC6 ios 2 3 25eC09 eos 12 5 poly(1) 51 4 25eC06 1 q1 19 3 18 pnp1 q2 20 12 18 pnp1 cin 3 2 3eC12 d1 3 1 dy d2 2 1 dy en 5 2 22 0 1 gn1 0 2 25 0 1eC5 gn2 0 3 28 0 1eC5 * * voltage noise source with flicker noise dn1 21 22 den dn2 22 23 den vn1 21 0 dc 2 vn2 0 23 dc 2 * * current noise source with flicker noise dn3 24 25 din dn4 25 26 din vn3 24 0 dc 2 vn4 0 26 dc 2 *
op113/OP213/op413 C16C rev. b c1805C18C6/93 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 8-lead plastic dip (n-8) 0.160 (4.06) 0.115 (2.93) 0.130 (3.30) min 0.210 (5.33) max 0.015 (0.381) typ 0.430 (10.92) 0.348 (8.84) 0.280 (7.11) 0.240 (6.10) 4 5 8 1 0.070 (1.77) 0.045 (1.15) 0.022 (0.558) 0.014 (0.356) 0.325 (8.25) 0.300 (7.62) 0? 15? 0.100 (2.54) bsc 0.015 (0.381) 0.008 (0.204) seating plane 0.195 (4.95) 0.115 (2.93) 8-lead narrow-body (so-8) seating plane 4 5 8 1 0.0688 (1.75) 0.0532 (1.35) 0.1574 (4.00) 0.1497 (3.80) 0.2440 (6.20) 0.2284 (5.80) 0.1968 (5.00) 0.1890 (4.80) 0.0192 (0.49) 0.0138 (0.35) 0.0500 (1.27) bsc 0.0098 (0.25) 0.0040 (0.10) 0.0098 (0.25) 0.0075 (0.19) 45? 0.0196 (0.50) 0.0099 (0.25) 0.0500 (1.27) 0.0160 (0.41) 0? 8 14-lead plastic dip (n-14) pin 1 1 14 8 7 0.325 (8.25) 0.300 (7.62) 0.210 (5.33) max 0.160 (4.06) 0.115 (2.92) 0.022 (0.558) 0.014 (0.36) 0.100 (2.54) bsc 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) min 015 0.015 (0.38) 0.008 (0.20) 0.280 (7.11) 0.240 (6.10) 0.015 (0.381) min 0.795 (20.19) 0.725 (18.41) 1

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